MEDIATE has recently participated in the RISC-V summit, held in Paris between the 12th and 15th of May, 2025 (more details). We had the opportunity to present one of the key MEDIATE technologies titled “HW-extended Containers on FPGA-based RISC-V SoC” that will become part of the framework and exchange ideas and know-how with various other experts in the field of RISC-V hardware design.
This paper describes a technology that brings together three key elements of reconfigurable hardware (FPGAs) prototyping, namely, Docker containers, RISC-V architectures, and runtime (dynamic) partial reconfiguration. The work envisaged serves the purpose of further expanding FPGA capabilities by allowing these processing platforms to support state-of-the-art development of prototypes with RISC-V soft-cores at their centre. The RISC-V processor features an Operating System (OS) that fully supports the execution of HW-extended Docker containers, which in turn contain all the necessary libraries, software, firmware and bitstreams for the implementation and utilisation of accelerator cores/modules within the reconfigurable fabric of the FPGA. Hence, different Docker containers, representing separate services and clients, will be able to deploy on-demand part of their functionality directly into the FPGA fabric benefiting from the parallel execution capabilities that this type of technology has to offer while the overall system will be based on a soft instance of a RISC-V processor core.
The MEDIATE framework is going to use RISC-V-based subsystems at the Sentinel level, complemented by hardware modules/accelerators that can be dynamically reconfigured in-field. The basis for this technology has already began development and it was presented at the summit, offering the opportunity to discuss its characteristics as well as bounce off ideas from engineers and designers offering invaluable insight as to the validity of our methodology as well as cultivating professional relationships for future research activities.